1. Field of the Invention
The field of the invention relates to semiconductor technology, and specifically to structure to monitor arcing between metal layers. More specifically, the present invention addresses charge-induced defects through adequate test structures that can be easily implemented in back-end-of-line processing.
2. Description of Related Art
Integrated circuit chips are exposed to various potential differences during processing making them vulnerable to charge induced damage. For example, silicon-on-insulator (SOI) technology in 300 mm semiconductor fabrication is prone to arcing damage and shorting. The primary problem from this phenomenon is defects caused by sprays of foreign material (debris) and the discharge damage itself. Damage to gates within the chip may also cause the chip to be nonfunctional. One of the mechanism by which charge accumulated on the wafer in the SOI technologies are discharged is generally through a guard ring, which is connected to the substrate and thus ground via the body (BI) contact through the buried oxide layer. The potential difference created by both the floating circuit net and the crack stop, which is connected to the substrate through the BI contact, increases as thicker dielectric stacks are fabricated through back-end-of-line (BEOL) processing. The greater potential build-up causes arcing or dielectric breakdown between the layers that typically results in electrical shorting and damage.
The primary method of detecting this type of charge damage has been historically through expensive and time-consuming optical inspection techniques. Since the defect normally manifests itself as an intermittent problem, it is difficult without testing to diagnosis a large sample size of components. Furthermore, the defect is generally detectable with optical inspection only if a large discharge is generated. More subtle problems will often remain undetected. Consequently, there remains a need in the industry to provide a test structure that allows the discharge to be detected more readily through standard in-line test methods.
Charge damage has been a key yield detractor in 90 nm technology. The absence of a suitable structure for monitoring this yield-detracting mechanism through electrical test prevents a manufacturer from employing an early detection scheme. As such, the manufacture is often unaware of the problem until a significant amount of hardware has been impacted by this failure mode. The present invention attempts to address charge-induced defects through adequate test structures that can be easily implemented.